COMP32211 - Implementing System-on-Chip Designs
The 'official' syllabus is: COMP32211.
Note: this module was formerly COMP32212. The change in code reflects a change in the semester of presentation, not any substantial difference to the syllabus. COMP32212 past exam. papers are still relevant.
COMP32212 was designed to follow the module COMP32111 which is no longer run. Some augmentation was necessary from years previous to 2014; most changes affect the laboratory and a more substantial manual has been produced. Except from the historic view, this should not affect the experience of the module.
The ultimate goal of any hardware design is a physical implementation. This course covers the translation of algorithms into a realisable hardware design. The practical part of the course develops higher level models into Verilog HDL and thence to an FPGA. In the lectures the process of mapping designs to ASICs is studied with emphasis on practicalities such as trading chip area, delays, power, etc. to meet a specification. Emphasis is also given to areas which are used extensively in the practical work, particularly simulation, debugging and verification.
A student completing this course should:
- have a working knowledge of Verilog for simulation and synthesis
- have taken a realistic digital design through to an implementation
- have an appreciation of many of the processes needed for VLSI manufacture
- have experienced a wide variety of CAD tools
The practical work develops a part on an SoC which is then integrated into a larger design and demonstrated using an FPGA implementation. Other topics relating to the targetting of designs onto custom silicon are covered in the lectures.
Lecture notes (2018 vintage)
- Display systems
- Verilog Revision
- Design tradeoffs
- Future trends
The 2017 manual - which is basically the same
as the previous year - is here. Only the cover has changed for the current year.
The C++ models supporting the labs. are available at file:///opt/info/courses/COMP32211/C_models/COMP32211_CPP.tar from a CS machine.
Locally developed hardware allows the user realise an FPGA implementation of a design within the scope of the laboratory.
Past exam. papers
- 2010-1 Exam paper
- 2011-2 Exam paper
- 2012-3 Exam paper
- 2013-4 Exam paper
- 2014-5 Exam paper
- 2015-6 Exam paper
- 2016-7 Exam paper
- 2017-8 Exam paper
- 2018-9 Exam paper
There has been no substantive change in syllabus over this period although there has been a slight raising of the abstraction levels in the VLSI sections.
The exam. style was altered under fiat to remove optional questions from January 2018.
Previous lecture notes (2013 vintage)
These cover some of the subjects differently (and, perhaps in more detail). They are primarily included for reference w.r.t. past exam papers.
None at this time.